As part of the PRACE-6IP project managed for the University by Dr. Varrette and Dr. Krishnasamy, several Best Practice Guides and White Papers are expected to be contributed to by HPC experts involved in the project. They are meant to be useful for all HPC practitioners worldwide thus are also valuable for the ULHPC community.
Here is a recap of the guides released so far holding our contributions:
2021 PRACE Best Practice Guide on “Modern Accelerators”
Announcement for this report was also done on Scientic Computing World, a global publication dedicated to the computing and information technology needs of scientists and engineers.
Abstract: Hardware accelerators offer certain advantages over general-purpose Central Processing Units (CPUs) as they provide a greater computational throughput when applications exhibit high degrees of data parallelism, due to their highly parallel architectural design and high-bandwidth memory systems. These specialized chips are usually more energy-efficient, i.e. are capable of delivering much higher compute performance as compared to CPUs at the same power cost. These characteristics make accelerator technologies appealing both for system vendors and users. The PRACE Best Practice Guide (BPG) on “Modern Accelerators” follows the style of previously published 2020 guide on “Modern Processors” we also contributed to, and provides an update on certain contemporary accelerator technologies, again, in a hybrid fashion of a field guide and a textbook. More specifically, this guide starts with introducing the architectures of considered accelerator technologies, namely:
- Graphics Processing Units (GPUs)
- Field-Programmable Gate Arrays (FPGAs)
- Vector processors
This is then followed by a discussion on their suitability for different HPC applications, and a description of their accompanying emerging programming models (e.g. CUDA, SYCL, HIP, etc.) and development environments. This BPG then outlines certain hints and best practices for application porting and tuning built upon the available literature and the expertise of authors involved.
Finally, the guide provides a brief information on the available hardware infrastructure at PRACE HPC sites featuring the discussed accelerator technologies, and concludes with a description of the case applications used.
2021 PRACE White Paper: Quantum Computing
Abstract
Quantum computers have the potential to bring forth a major breakthrough in scientific computing. The foreseen increase in computational efficiency offered by quantum computing is of such magnitude that, despite being in its infancy, it is already being coupled with traditional high-performance computing technology. Here, we give an overview of quantum computing, the present state of affairs, and future scenarios. Europe has a unique opportunity to create world-leading supercomputing infrastructures incorporating quantum technology, by capitalising on the established expertise of European HPC centres in conjunction with the emerging European quantum ecosystem. This requires dedicated and sustained funding for quantum hardware and software developments, as well as for education. In addition, coordinated efforts and support for early adoption of quantum computing in academia and industry are essential.
2020 PRACE Best Practice Guide
Abstract
This Best Practice Guide (BPG) extends the previously developed series of BPGs by providing an update on new technologies and systems for the further support of European High Performance Computing (HPC) user community in achieving a remarkable performance of their large-scale applications. It covers existing systems and aims to provide support for scientists to port, build and run their applications on these systems. While some benchmarking is part of this guide, the results provided are mainly an illustration of the different systems characteristics, and should not be used as guides for the comparison of systems presented nor should be used for system procurement considerations. Procurement [2] and benchmarking [3] are well covered by other PRACE work packages and are out of this BPG’s discussion scope. This BPG document has grown to be a hybrid of field guide and a textbook approach. The system and processor coverage provide some relevant technical information for the users who need a deeper knowledge of the system in order to fully utilise the hardware. While the field guide approach provides hints and starting points for porting and building scientific software. For this, a range of compilers, libraries, debuggers, performance analysis tools, etc. are covered. While recommendation for compilers, libraries and flags are covered we acknowledge that there is no magic bullet as all codes are different. Unfortunately there is often no way around the trial and error approach. Some in-depth documentation of the covered processors is provided. This includes some background on the inner workings of the processors considered; the number of threads each core can handle; how these threads are implemented and how these threads (instruction streams) are scheduled onto different execution units within the core. In addition, this guide describes how the vector units with different lengths (256, 512 or in the case of SVE - variable and generally unknown until execution time) are implemented. As most of HPC work up to now has been done in 64 bit floating point the emphasis is on this data type, specially for vectors. In addition to the processor executing units, memory in its many levels of hierarchy is important. The different implementations of Non-Uniform Memory Access (NUMA) are also covered in this BPG. The guide gives a description of the hardware for a selection of relevant processors currently deployed in some PRACE HPC systems. It includes ARM64 (Huawei/HiSilicon and Marvell) and x86-64 (AMD and Intel). It provides information on the programming models and development environment as well as information about porting programs. Furthermore it provides sections about strategies on how to analyze and improve the performance of applications. While this guide does not provide an update on all recent processors, some of the previous BPG releases do cover other processor architectures not discussed in this guide (e.g. Power architecture) and should be considered as a staring point for work. This guide aims also to increase the user awareness on energy and power consumption of individual applications by providing some analysis on usefulness of maximum CPU frequency scaling based on the type of application considered (e.g. CPU-bound, memory-bound, etc.).